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| White Electronic Designs 128KX32 SRAM/FLASH MODULE FEATURES Access Times of 25ns (SRAM) and 70, 90 and 120ns (FLASH) Packaging: * 66-pin, PGA Type, 1.385 inch square HIP, Hermetic Ceramic HIP (Package 402) 128Kx32 SRAM 128Kx32 5V Flash Organized as 128Kx32 of SRAM and 128Kx32 of Flash Memory with common Data Bus Low Power CMOS Commercial, Industrial and Military Temperature Ranges TTL Compatible Inputs and Outputs Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation Weight - 13 grams typical WSF128K32-XH2X PRELIMINARY* FLASH MEMORY FEATURES 10,000 Erase/Program Cycles Sector Architecture * 8 equal size sectors of 16K bytes each * Any combination of sectors can be concurrently erased. Also supports full chip erase 5 Volt Programming; 5V 10% Supply Embedded Erase and Program Algorithms Hardware Write Protection Page Program Operation and Internal Program Control Time. * This product is under development, not fully characterized, and is subject to change without notice. Note: Programming information available upon request. FIGURE 1 - PIN CONFIGURATION FOR WSF128K32-XH2X Top View 1 I/O8 I/O9 I/O10 A14 A16 A11 A0 NC I/O0 I/O1 I/O2 11 22 12 FWE2# SWE2# GND I/O11 A10 A9 A15 VCC FCS# SCS# I/O3 33 23 I/O15 I/O14 I/O13 I/O12 OE# NC FWE1# I/O7 I/O6 I/O5 I/O4 I/O24 I/O25 I/O26 A7 A12 SWE1# A13 A8 I/O16 I/O17 I/O18 44 34 VCC SWE4# FWE4# I/O27 A4 A5 A6 FWE3# SWE3# GND I/O19 55 45 I/O31 I/O30 I/O29 I/O28 A1 A2 A3 FWE1# SWE1# Pin Description 56 D0-31 A0-16 SWE1-4# SCS# OE# VCC GND NC FWE1-4# FCS# Data Inputs/Outputs Address Inputs SRAM Write Enable SRAM Chip Selects Output Enable Power Supply Ground Not Connected Flash Write Enable Flash Chip Select Block Diagram FWE2# SWE2# FWE3# SWE3# FWE4# SWE4# OE# A0-16 SCS# FCS# I/O23 I/O22 I/O21 I/O20 66 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM 128K x 8 Flash 128K x 8 SRAM I/O0-7 I/O8-15 I/O16-23 I/O24-31 White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Junction Temperature Supply Voltage Symbol TA TSTG VG TJ VCC Min -55 -65 -0.5 -0.5 Max +125 +150 7.0 150 7.0 Unit C C V C V SCS# H L L L OE# X L H X WSF128K32-XH2X PRELIMINARY SRAM TRUTH TABLE SWE# X H H L Mode Standby Read Read Write Data I/O High Z Data Out High Z Data In Power Standby Active Active Active NOTE: 1. FCS# must remain high when SCS# is low. Parameter Flash Data Retention Flash Endurance (write/erase cycles) 10 years 10,000 Parameter OE# capacitance F/S WE1-4# capacitance F/S CS# capacitance D0-31 capacitance A0-16 capacitance CAPACITANCE Ta = +25C Symbol COE CWE CCS CI/O CAD Conditions Max Unit VIN = 0 V, f = 1.0 MHz 80 pF VIN = 0 V, f = 1.0 MHz 30 pF VIN = 0 V, f = 1.0 MHz 50 pF VIN = 0 V, f = 1.0 MHz 30 pF VIN = 0 V, f = 1.0 MHz 80 pF NOTE: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 -0.5 Max 5.5 VCC + 0.3 +0.8 Unit V V V This parameter is guaranteed by design but not tested. DC CHARACTERISTICS VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current SRAM Operating Supply Current x 32 Mode Standby Current SRAM Output Low Voltage SRAM Output High Voltage Flash VCC Active Current for Read (1) Flash VCC Active Current for Program or Erase (2) Flash Output Low Voltage Flash Output High Voltage Flash Output High Voltage Flash Low VCC Lock Out Voltage Symbol ILI ILO ICCx32 ISB VOL VOH ICC1 ICC2 VOL VOH1 VOH2 VLKO Conditions VCC = 5.5, VIN = GND to VCC SCS# = VIH, OE# = VIH, VOUT = GND to VCC SCS# = VIL, OE# = FCS# = VIH, f = 5MHz, VCC = 5.5 FCS# = SCS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 IOL = 8mA, VCC = 4.5 IOH = -4.0mA, VCC = 4.5 FCS# = VIL, OE# = SCS# = VIH FCS# = VIL, OE# = SCS# = VIH IOL = 8.0mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 IOH = -100 A, VCC = 4.5 Min Max 10 10 670 80 0.4 220 280 0.45 0.85 x VCC VCC -0.4 3.2 Unit A A mA mA V V mA mA V V V V 2.4 NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs SRAM AC CHARACTERISTICS VCC = 5.0V, -55C TA +125C Parameter Read Cycle Read Cycle Time Address Access Time Output Hold from Address Change Chip Select Access Time Output Enable to Output Valid Chip Select to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Symbol Min tRC tAA tOH tACS tOE tCLZ1 tOLZ1 tCHZ1 tOHZ1 25 25 0 25 15 3 0 12 12 -25 Max ns ns ns ns ns ns ns ns ns Units Parameter Write Cycle WSF128K32-XH2X PRELIMINARY SRAM AC CHARACTERISTICS VCC = 5.0V, -55C TA +125C Symbol Min tWC tCW tAW tDW tWP tAS tAH tOW1 tWHZ1 tDH 25 20 20 15 20 3 0 3 15 0 -25 Max ns ns ns ns ns ns ns ns ns ns Units 1. This parameter is guaranteed by design but not tested. Write Cycle Time Chip Select to End of Write Address Valid to End of Write Data Valid to End of Write Write Pulse Width Address Setup Time Address Hold Time Output Active from End of Write Write Enable to Output in High Z Data Hold from Write Time 1. This parameter is guaranteed by design but not tested. FIGURE 2 - AC TEST CIRCUIT AC Test Conditions I OL Current Source D.U.T. C eff = 50 pf VZ 1.5V (Bipolar Supply) Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V I OH Current Source Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 . VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WSF128K32-XH2X PRELIMINARY FIGURE 3 - SRAM TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA tRC ADDRESS SCS# tACS tAA tOH SOE# tCHZ tCLZ tOE tOLZ DATA I/O HIGH IMPEDANCE DATA I/O PREVIOUS DATA VALID DATA VALID tOHZ DATA VALID READ CYCLE 1, (SCS# = OE# = VIL, SWE# = FCS# = VIH) READ CYCLE 2, (SWE# = FCS# = VIH) FIGURE 4 - SRAM WRITE CYCLE - SWE# CONTROLLED tWC ADDRESS tAW tCW SCS# tAH tAS SWE# tWP tOW tWHZ tDW DATA VALID tDH DATA I/O WRITE CYCLE 1, SWE# CONTROLLED (FCS# = VIH) FIGURE 5 - SRAM WRITE CYCLE - SCS# CONTROLLED tWC ADDRESS tAS SCS# tAW tCW tAH tWP SWE# tDW DATA I/O DATA VALID tDH WRITE CYCLE 2, SCS# CONTROLLED (FCS# = VIH) White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs VCC = 5.0V, -55C TA +125C Parameter Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (min) Chip and Sector Erase Time Read Recovery Time Before Write VCC Set-up Time Chip Programming Time Output Enable Setup Time Output Enable Hold Time (1) 1. For Toggle and Data# Polling. tOES tOEH 0 10 tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHEH tWHWL tWHWH1 tWHWH2 tGHWL tVCS Symbol Min tWC tCS tWP tAS tDS tDH tAH tCH tWPH 70 0 45 0 45 0 45 0 20 14 2.2 0 50 12.5 0 10 60 -70 Max Min 90 0 45 0 45 0 45 0 20 14 2.2 0 50 -90 WSF128K32-XH2X PRELIMINARY FLASH AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, FWE# CONTROLLED -120 Max Min 120 0 50 0 50 0 50 0 20 14 60 2.2 0 50 12.5 0 10 12.5 60 Max ns ns ns ns ns ns ns ns ns s sec s s sec ns ns Unit FLASH AC CHARACTERISTICS - READ ONLY OPERATIONS VCC = 5.0V, -55C TA +125C Parameter Read Cycle Time Address Access Time Chip Select Access Time OE# to Output Valid Chip Select to Output High Z (1) OE# High to Output High Z (1) Output Hold from Address, FCS# or OE# Change, whichever is first 1. Guaranteed by design, not tested. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Symbol Min tRC tACC tCE tOE tDF tDF tOH 0 70 70 70 35 20 20 0 -70 Max Min 90 90 90 40 25 25 0 -90 Max Min 120 120 120 50 30 30 -120 Max ns ns ns ns ns ns ns Unit White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs VCC = 5.0V, -55C TA +125C Parameter Write Cycle Time FWE# Setup Time FCS# Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time FWE# Hold from FWE# High FCS# Pulse Width High Duration of Programming Operation Duration of Erase Operation Read Recovery before Write Chip Programming Time tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHWH tEHEL tWHWH1 tWHWH2 tGHEL WSF128K32-XH2X PRELIMINARY FLASH AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS, FCS# CONTROLLED Symbol Min tWC tWS tCP tAS tDS tDH tAH tWH tCPH 70 0 35 0 30 0 45 0 20 14 2.2 0 12.5 60 -70 Max Min 90 0 45 0 45 0 45 0 20 14 2.2 0 -90 Max Min 120 0 50 0 50 0 50 0 20 14 60 2.2 0 12.5 -120 Max Unit ns ns ns ns ns ns ns ns ns s 60 sec ns 12.5 sec White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WSF128K32-XH2X PRELIMINARY FIGURE 6 - AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS tRC Addresses tACC FCS# tDF OE# tOE Addresses Stable FWE# tCE tOH High Z Outputs High Z Output Valid NOTE: SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WSF128K32-XH2X PRELIMINARY FIGURE 7 - WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE# CONTROLLED Data# Polling Addresses 5555H tWC FCS# tGHWL OE# tWP FWE# tCS tWPH tDH Data tDS tOH A0H PD tOE tDF tWHWH1 tAS PA tAH PA tRC D7# DOUT 5.0 V tCE NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WSF128K32-XH2X PRELIMINARY FIGURE 8 - AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY tAS Addresses 5555H tAH 2AAAH 5555H 5555H 2AAAH SA FCS# tGHWL OE# tWP FWE# tWPH tCS Data tDS tDH AAH 55H 80H AAH 55H 10H/30H VCC tVCS Notes: 1. SA is the sector address for Sector Erase. 2. SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WSF128K32-XH2X PRELIMINARY FIGURE 9 - AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS FOR FLASH MEMORY FCS# tCH tDF tOE OE# tOEH FWE# tCE tOH D7 tWHWH 1 or 2 D0-D6 D0-D6 = Invalid tOE D7 tWHWH 1 or 2 D7 D7 Valid Data High Z D0-D7 Valid Data D7# D7 = Valid Data High Z Note: SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WSF128K32-XH2X PRELIMINARY FIGURE 10 - WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS# CONTROLLED Data# Polling Addresses 5555H tWC FWE# tGHEL OE# tCP FCS# tWS tWHWH1 tAS PA tAH PA tCPH tDH Data tDS A0H PD D7# DOUT 5.0 V NOTES: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7# is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence. 6. SCS# = VIH White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WSF128K32-XH2X PRELIMINARY PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2) 35.2 (1.385) 0.38 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 5.7 (0.223) MAX 3.81 (0.150) 0.1 (0.005) 2.54 (0.100) TYP 1.27 (0.050) 0.1 (0.005) 0.76 (0.030) 0.1 (0.005) 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION W S F 128K32 - XX H2 X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55C to +125C -40C to +85C 0C to +70C PACKAGE TYPE: H2 = Ceramic Hex In-line Package, HIP (Package 402) ACCESS TIME (ns) 22 = 25ns SRAM and 120ns FLASH 29 = 25ns SRAM and 90ns FLASH 27 = 25ns SRAM and 70ns FLASH ORGANIZATION, 128K x 32 Flash PROM SRAM WHITE ELECTRONIC DESIGNS CORP. White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 4 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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